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?2007 silicon storage technology, inc. s71259-04-000 1/07 1 the sst logo, superflash, and flashflex are registered trademarks of silicon storage technology, inc. these specifications are subject to change without notice. data sheet features: ? 8-bit 8051-compatible microcontroller (mcu) with embedded superflash memory ? fully software compatible ? development toolset compatible ? pin-for-pin package compatible ? sst89e5xrc operation ? 0 to 33mhz at 5v ? total 512 byte internal ram (256 byte by default + 256 byte enabled by software) ? single block superflash eeprom ? sst89e54rc: 16 kbyte primary partition + 1 kbyte secondary partition ? sst89e52rc: 8 kbyte primary partition + 1 kbyte secondary partition ? primary partition is divided into four pages ? secondary partition has one page ? individual page security lock ? in-system programming (isp) ? in-application programming (iap) ? small-sector architecture: 128-byte sector size ? support external address range up to 64 kbyte of program and data memory ? three high-current port 1 pins (16 ma each) ? three 16-bit timers/counters ? full-duplex, enhanced uart ? framing error detection ? automatic address recognition ? eight interrupt sources at 4 priority levels ? programmable watchdog timer (wdt) ? four 8-bit i/o ports (32 i/o pins) ? second dptr register ? low emi mode (inhibit ale) ? standard 12 clocks per cycle, the device has an option to double the speed to 6 clocks per cycle. ? ttl- and cmos-compatible logic levels ? low power modes ? power-down mode with external interrupt wake-up ? idle mode ? selectable operation clock ? divide down to 1/4, 1/16, 1/256, or 1/1024th ? temperature ranges: ? commercial (0c to +70c) ? packages available ? 40-pin pdip ? 44-lead plcc ? all non-pb (lead-free) devices are rohs compliant product description the sst89e52rc / sst89e54rc are members of the flashflex family of 8-bit mi crocontroller products designed and manufactured with sst?s patented and proprietary superflash cmos semiconductor process technology. the split-gate cell design and thick-oxide tunneling injector offer significant co st and reliability benefits for our custom- ers.the devices use the 8051 instruction set and are pin- for-pin compatible with standard 8051 microcontroller devices. the device comes with 17/9 kbyte of on-chip flash eeprom program memory which is divided into 2 inde- pendent program memory partitions. the primary partition occupies 16/8 kbyte of internal program memory space and the secondary partition occupies 1 kbyte of internal program memory space. the flash memory can be programmed via a standard 87c5x otp eprom programmer fitted with a special adapter and firmware for sst?s devices. during power-on reset, the devices can be configured as either a slave to an external host for source code storage or a master to an external host for an in-system programming (isp) opera- tion. the devices are designed to be programmed in-sys- tem on the printed circuit board for maximum flexibility. an example of the bootstrap loader (bsl) in memory, demon- strating initial user program code loading or subsequent user code updating via an isp operation, is provided on the sst website. the sample bsl is for the user?s reference only; sst does not guarantee its functionality. in addition to 17/9 kbyte of superflash eeprom program memory on-chip and 512 x8 bits of on-chip ram, the device can address up to 64 kbyte of external program memory and up to 64 kbyte of external ram. the highly-reliable, patented sst superflash technology and memory cell architecture have a number of important advantages for designing and manufacturing flash eeproms. these advantages translate into significant cost and reliability benefits for our customers. flashflex mcu sst89e52rc / sst89e54rc
2 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 table of contents features: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 list of tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.0 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.0 pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.0 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 program flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 data ram memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 expanded data ram addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 dual data pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5 special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.0 flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1 product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 in-application programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3 in-system programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.0 timers/counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 timer set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 programmable clock-out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.0 serial i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 full-duplex, enhanced uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.0 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 watchdog timer mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 pure timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.4 feed sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.5 power saving considerations for using the watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.0 security lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.1 chip-level security lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.2 page-level security lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.3 read operation under lock condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.0 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2 boot sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.3 interrupt priority and polling sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.0 power-saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.2 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
data sheet flashflex mcu sst89e52rc / sst89e54rc 3 ?2007 silicon storage technology, inc. s71259-04-000 1/07 11.0 system clock and clock options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.1 clock input options and recommended ca pacitor values for oscillator . . . . . . . . . . . . . . . . . . . . . . 44 11.2 clock doubling option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.3 clock divider option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.0 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.1 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12.2 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13.0 product ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14.0 packaging diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 list of figures figure 1: functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2-1: pin assignments for 40-pin pdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2-2: pin assignments for 44-lead plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3-1: internal and external data memory structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 figure 3-2: program memory organization and code security protection. . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3-3: dual data pointer organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6-1: framing error block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 6-2: uart timings in mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 6-3: uart timings in modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 7-1: block diagram of programmable watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 9-1: power-on reset circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 9-2: boot sequence flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 9-3: hardware pin setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 9-4: interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 11-1: oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 12-1: external program memory read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 figure 12-2: external data memory read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 12-3: external data memory write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 12-4: external clock drive waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 12-5: shift register mode timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 12-6: ac testing input/output test waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 12-7: float waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 12-8: a test load example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 12-9: i dd test condition, active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 12-10: i dd test condition, idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 12-11: i dd test condition, power-down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 14-1: 40-pin plastic dual in-line pins (pdip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 14-2: 44-lead plastic lead chip carrier (plcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 list of tables table 2-1: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3-1: external data memory rd#, wr# with extram bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3-2: flashflex sfr memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3-3: cpu related sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3-4: flash memory programming sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3-5: watchdog timer sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3-6: feed sequence sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3-7: timer/counters sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3-8: interface sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3-9: clock option sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4-1: product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 4-2: default boot vector settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 4-3: iap commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5-1: timer/counter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5-2: timer/counter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5-3: timer/counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 9-1: boot vector address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 9-2: interrupt polling sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 10-1: power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 11-1: recommended values for c1 and c2 by crystal type . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 11-2: clock doubling features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 12-1: operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 12-2: reliability ch aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 12-3: ac conditions of test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 12-4: recommended system power-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 12-5: pin impedance (ta=25 c, f=1 mhz, other pins open) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 12-6: dc characteristics for sst89e5xrc: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 12-7: ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 12-8: external clock drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 12-9: serial port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 12-10: flash memory programming/verification parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 14-1: revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
data sheet flashflex mcu sst89e52rc / sst89e54rc 5 ?2007 silicon storage technology, inc. s71259-04-000 1/07 1.0 functional blocks figure 1: functional block diagram 8 interrupts superflash eeprom primary partition 16k x8 for sst89x54rc 8k x8 for sst89x52rc secondary partition 1k x8 i/o i/o i/o i/o watchdog timer interrupt control 8051 cpu core ram 512 x8 security lock i/o port 0 i/o port 1 i/o port 2 i/o port 3 8-bit enhanced uart timer 0 (16-bit) timer 1 (16-bit) timer 2 (16-bit) 8 8 8 8 1259 b1.3 flash control unit 8 oscillator alu, acc, b-register, instruction register, program counter, timing and control
6 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 2.0 pin assignments figure 2-1: pin assignments for 40-pin pdip figure 2-2: pin assignments for 44-lead plcc 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 (t2) p1.0 (t2 ex) p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 rst (rxd) p3.0 (txd) p3.1 (int0#) p3.2 (int1#) p3.3 (t0) p3.4 (t1) p3.5 (wr#) p3.6 (rd#) p3.7 xtal2 xtal1 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 v dd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea# ale/prog# psen# p2.7 (a15) p2.6 (a14) p2.5 (a13) p2.4 (a12) p2.3 (a11) p2.2 (a10) p2.1 (a9) p2.0 (a8) 40-pin pdip top view 1259 40-pdip pi p1.1 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 p1.5 p1.6 p1.7 rst (rxd) p3.0 nc (txd) p3.1 (int0#) p3.2 (int1#) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea# nc ale/prog# psen# p2.7 (a15) p2.6 (a14) p2.5 (a13) 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 p1.4 p1.3 p1.2 p1.1 (t2 ex) p1.0 (t2) nc v dd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) (wr#) p3.6 (rd#) p3.7 xtal2 xtal1 v ss nc (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 44-lead plcc top view 1259 44-plcc nj p3.1
data sheet flashflex mcu sst89e52rc / sst89e54rc 7 ?2007 silicon storage technology, inc. s71259-04-000 1/07 2.1 pin descriptions table 2-1: pin descriptions (1 of 2) symbol type 1 name and functions p0[7:0] i/o port 0: port 0 is an 8-bit open drain bi-directional i/o port. as an output port each pin can sink several ls ttl inputs. port 0 pins that have ?1?s written to them float, and in this state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external code and data memory. in this application, it uses strong internal pull-ups when transitioning to ?1?s. port 0 also receives the code bytes during the external host mode programming, and outpu ts the code bytes during the external host mode verification. external pull-ups are required during program verification or as a general purpose i/o port. p1[7:0] i/o with internal pull-up port 1: port 1 is an 8-bit bi-directional i/o port with internal pull-ups. the port 1 output buffers can drive ls ttl inputs. port 1 pins are pulled high by the internal pull-ups when ?1?s are writ- ten to them and can be used as i nputs in this state. as inputs, port 1 pins that are externally pulled low will source current (i il , see table 12-6) because of the internal pull-ups. p1[5, 6, 7] have high current drive of 16 ma. port 1 also receives the low-order address byte during the external host mode programming and verification. p1[0] i/o t2: external count input to timer/counte r 2 or clock-out from timer/counter 2 p1[1] i t2ex: timer/counter 2 capture/reload trigger and direction control p1[2] i/o gpio p1[3] i/o gpio p1[4] i/o gpio p1[5] i/o gpio p1[6] i/o gpio p1[7] i/o gpio p2[7:0] i/o with internal pull-up port 2: port 2 is an 8-bit bi-directional i/o port with internal pull-ups. port 2 pins are pulled high by the internal pull-ups when ?1?s are written to them and can be used as inputs in this state. as inputs, port 2 pins that are externally pulled low will source current (i il , see table 12-6) because of the internal pull-ups. port 2 sends the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit address (movx@dptr). in this applicat ion, it uses strong internal pull-ups when transitioning to ?1?s. port 2 also receives the high-order address byte during the external host mode programming and verification. p3[7:0] i/o with internal pull-up port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. the port 3 output buffers can drive ls ttl inputs. port 3 pins are pulled high by the internal pull-ups when ?1?s are writ- ten to them and can be used as i nputs in this state. as inputs, port 3 pins that are externally pulled low will source current (i il , see table 12-6) because of the internal pull-ups. port 3 also receives the high-order address byte during the external host mode programming and verifi- cation. p3[0] i rxd: universal asynchronous receiver/t ransmitter (uart) - receive input p3[1] o txd: uart - transmit output p3[2] i int0#: external interrupt 0 input p3[3] i int1#: external interrupt 1 input p3[4] i t0: external count input to timer/counter 0 p3[5] i t1: external count input to timer/counter 1 p3[6] o wr#: external data memory write strobe p3[7] o rd#: external data memory read strobe
8 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 psen# i/o program store enable: psen# is the read strobe to external program. when the device is executing from internal program memory, psen# is inactive (high). when the device is exe- cuting code from external program memory, psen# is activated twice each machine cycle, except that two psen# activations are skipped during each access to external data memory. a forced high-to-low input tran sition on the psen# pin while the rst input is continually held high for more than 10 machine cycles will cause the device to enter external host mode pro- gramming. rst i reset: while the oscillator is runnin g, a ?high? logic state on this pin for two machine cycles will reset the device. if the psen# pin is driven by a high-to-low input transition while the rst input pin is held ?high,? the device will enter the external host mode, otherwise the device will enter the normal operation mode. ea# i external access enable: ea# must be connected to v ss in order to enable the device to fetch code from the external program memory. ea# must be strapped to v dd for internal pro- gram execution. however, disable-extern-boot (see section 8.0, ?security lock?) will disable ea#, and program execution is only possible from internal program memory. the ea# pin can tolerate a high voltage 2 of 12v. (see section 12.0, ?electrical specification?) ale/prog# i/o address latch enable: ale is the output signal for latching the low byte of the address dur- ing an access to external memory. this pin is also the programming pulse input (prog#) for flash programming. normally the ale 3 is emitted at a constant rate of 1/6 the crystal fre- quency 4 and can be used for external timing and clocking. one ale pulse is skipped during each access to external data memory. however, if ao is set to 1, ale is disabled. (see ?auxiliary register (auxr)? in section 3.5, ?special function registers?) nc i/o no connect xtal1 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 o crystal 2: output from the inverting oscillator amplifier. v dd i power supply v ss i ground t2-1.0 1259 1. i = input; o = output 2. it is not necessary to receive a 12v pr ogramming supply voltage during flash programming. 3.ale loading issue: when ale pin experienc es higher loading (>30pf) during the reset, the mcu may accidentally enter into mode s other than normal working mode. the solution is to add a pull-up resistor of 3-50 k to v dd , e.g. for ale pin. 4. for 6 clock mode, ale is emitted at 1/3 of crystal frequency. table 2-1: pin descriptions (continued) (2 of 2) symbol type 1 name and functions
data sheet flashflex mcu sst89e52rc / sst89e54rc 9 ?2007 silicon storage technology, inc. s71259-04-000 1/07 3.0 memory organization the device has separate address spaces for program and data memory. 3.1 program flash memory there are two internal flash memory partitions in the device. the primary flash memory partition (partition 0) has 16/8 kbyte. the secondary flash memory partition (parti- tion 1) has 1 kbyte. the total flash memory space of both partitions can be used as a contiguous code storage. the 16k/8k x8 primary flash partition is organized as 128/ 64 sectors, each sector consists of 128 bytes. the primary partition is divided into four logical pages as shown in fig- ure 3-2 the 1k x8 secondary flash partition is organized as 8 sec- tors, each sector consists also of 128 bytes. for both partitions, the 7 least significant program address bits select the byte within the sector. the remainder of the program address bits select the sector within the partition. 3.2 data ram memory the data ram has 512 bytes of internal memory. the first 256 bytes are available by default. the second 256 bytes are enabled by clearing the extram bit in the auxr reg- ister. the ram can be addressed up to 64 kbyte for exter- nal data memory. 3.3 expanded data ram addressing the sst89e5xrc have the capability of 512 bytes of ram. see figure 3-1. the device has four sections of internal data memory: 1. the lower 128 bytes of ram (00h to 7fh) are directly and indirectly addressable. 2. the higher 128 bytes of ram (80h to ffh) are indirectly addressable. 3. the special function registers (80h to ffh) are directly addressable only. 4. the expanded ram of 256 bytes (00h to ffh) is indirectly addressable by the move external instruction (movx) and clearing the extram bit. (see ?auxiliary register (auxr)? in section 3.5, ?special function registers?) since the upper 128 bytes occupy the same addresses as the sfrs, the ram must be accessed indirectly. the ram and sfrs space are physically separate even though they have the same addresses. when instructions access addresses in the upper 128 bytes (above 7fh), the mcu determines whether to access the sfrs or ram by the type of instruction given. if it is indirect, then ram is accessed. if it is direct, then an sfr is accessed. see the examples below. indirect access: mov @r0, #data ; r0 contains 90h register r0 points to 90h which is located in the upper address range. data in ?#data? is written to ram location 90h rather than port 1. direct access: mov 90h, #data ; write data to p1 data in ?#data? is written to port 1. instructions that write directly to the address write to the sfrs. to access the expanded ram, the extram bit must be cleared and movx instructions must be used. the extra 256 bytes of memory is physically located on the chip and logically occupies the first 256 bytes of external memory (addresses 000h to ffh). when extram = 0, the expanded ram is indirectly addressed using the movx instruction in combination with any of the registers r0, r1 of the selected bank or dptr. accessing the expanded ram does not affect ports p0, p3.6 (wr#), p3.7 (rd#), or p2. with extram = 0, the expanded ram can be accessed as in the following example. expanded ram access (indirect addressing only): movx @dptr, a ; dptr contains 0a0h dptr points to 0a0h and data in ?a? is written to address 0a0h of the expanded ram rather than external memory. access to external memory higher than ffh using the movx instruction will access external memory (0100h to ffffh) and will perform in the same way as the standard 8051, with p0 and p2 as data/address bus, and p3.6 and p3.7 as write and read timing signals. when extram = 1, movx @ri and movx @dptr will be similar to the standard 8051. using movx @ri pro- vides an 8-bit address with multiplexed data on port 0. other output port pins can be used to output higher order address bits. this provides external paging capabilities. using movx @dptr generates a 16-bit address. this allows external addressing up the 64k. port 2 provides the high-order eight address bits (dph), and port 0 multiplexes the low order eight address bits (dpl) with data. both movx @ri and movx @dptr generates the necessary
10 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 read and write signals (p3.6 - wr# and p3.7 - rd#) for external memory use. table 3-1 shows external data mem- ory rd#, wr# operation with extram bit. the stack pointer (sp) can be located anywhere within the 256 bytes of internal ram (lower 128 bytes and upper 128 bytes). the stack pointer may not be located in any part of the expanded ram. figure 3-1: internal and external data memory structure table 3-1: external data memory rd#, wr# with extram bit movx @dptr, a or movx a, @dptr movx @ri, a or movx a, @ri auxr addr < 0100h addr >= 0100h addr = any extram = 0 rd# / wr# not asserted rd# / wr# asserted rd# / wr# not asserted 1 1. access limited to eram address within 0 to 0ffh. extram = 1 rd# / wr# asserted rd# / wr# asserted rd# / wr# asserted t3-1.0 1259 000h ffh 00h ffh upper 128 bytes internal ram lower 128 bytes internal ram (indirect & direct addressing) (indirect addressing) (direct addressing) special function registers (sfrs) 80h ffh ffffh 000h external data memory ffh 0000h external data memory extram = 0 extram = 1 expanded ram 0100h (indirect addressing) ffffh (indirect addressing) (indirect addressing) 80h 7fh 1259 f01.0 expanded ram 256 bytes
data sheet flashflex mcu sst89e52rc / sst89e54rc 11 ?2007 silicon storage technology, inc. s71259-04-000 1/07 figure 3-2: program memory organization and code security protection 3.4 dual data pointers the device has two 16-bit data pointers. the dptr select (dps) bit in auxr1 determines which of the two data pointers is accessed. when dps=0, dptr0 is selected; when dps=1, dptr1 is selected. quickly switching between the two data pointers can be accomplished by a single inc instruction on auxr1. (see figure 3-3) 3.5 special function registers most of the unique features of the flashflex microcontroller family are controlled by bits in special function registers (sfrs) located in the sfr memory map shown in table 3- 2. individual descriptions of each sfr are provided and reset values indicated in tables 3-3 to 3-8. figure 3-3: dual data pointer organization 0000h 1fffh 0000h 3fffh 1259 f02.3 2kbyte page 2kbyte page 2kbyte page 2kbyte page 1kbyte page 4kbyte page 4kbyte page 4kbyte page 4kbyte page 1kbyte page sst89e54rc sst89e52rc primary partition primary partition secondary partition secondary partition external 64 kbyte ea# = 0 ffffh 0000h ea# = 1 ea# = 1 dpl 82h dps = 0 dptr0 dps = 1 dptr1 external data memory dps 1259 f03.0 dph 83h dptr0 dptr1 auxr1 / bit0
12 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 table 3-2: flashflex sfr memory map 8 bytes f8h ipa 1 1. bit addressable sfrs ffh f0h b 1 ipah f7h e8h iea 1 efh e0h acc 1 e7h d8h dfh d0h psw 1 spcr d7h c8h t2con 1 t2mod rcap2l rcap2h tl2 th2 cfh c0h wdtc 1 sfis1 c7h b8h ip 1 saden cosr bfh b0h p3 1 sfcf sfcm sfal sfah sfdt sfst iph b7h a8h ie 1 saddr afh a0h p2 1 pmc auxr1 a7h 98h scon 1 sbuf 9fh 90h p1 1 sfis0 97h 88h tcon 1 tmod tl0 tl1 th0 th1 auxr 8fh 80h p0 1 sp dpl dph wdtd pcon 87h t3-2.1 1259
data sheet flashflex mcu sst89e52rc / sst89e54rc 13 ?2007 silicon storage technology, inc. s71259-04-000 1/07 table 3-3: cpu related sfrs symbol description direct address bit address, symbol, or alternative port function reset value msb lsb acc 1 accumulator e0h acc[7:0] 00h b 1 b register f0h b[7:0] 00h psw 1 program status word d0h cy ac f0 rs1 rs0 ov f1 p 00h sp stack pointer 81h sp[7:0] 07h dpl data pointer low 82h dpl[7:0] 00h dph data pointer high 83h dph[7:0] 00h ie 1 interrupt enable a8h ea ec et2 es et1 ex1 et0 ex0 00h iea 1 interrupt enable a e8h - ewd - - - - - - x0xxxxxxb ip 1 interrupt priority reg b8h - - pt2 ps pt1 px1 pt0 px0 x0000000b iph interrupt priority reg high b7h - ppch pt2h psh pt1h px1h pt0h px0h x0000000b ipa 1 interrupt priority reg a f8h - pwd - - - - - - x0xxxxxxb ipah interrupt priority reg a high f7h - pwdh - - - - - - x0xxxxxxb pcon power control 87h smod1 smod0 - pof gf1 gf0 pd idl 00x10000b auxr auxiliary reg 8eh - - - - - - extram ao xxxxxxx00b auxr1 auxiliary reg 1 a2h - - - - gf2 0 - dps xxxx00x0b pmc power management control register a1h - - wdu tct tct2 pb2 pb1 uart xx000000b t3-3.1 1259 1. bit addressable sfrs
14 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 table 3-4: flash memory programming sfrs symbol description direct address bit address, symbol, or alternative port function reset value msb lsb sfcf superflash configuration b1h cmd_ status iapen - hwiap - sfst_sel 10000000b sfcm superflash command b2h - fcm[6:0] 00h sfal superflash address low b3h superflash low order byte address register a 7 to a 0 (sfal) 00h sfah superflash address high b4h superflash high order byte address register a 15 to a 8 (sfah) 00h sfdt superflash data b5h superflash data register 00h sfst superflash status b6h sfst_sel= 0h manufacturer?s id bfh sfst_sel= 1h device id0 (f7h indicates device id1 is real id) sfst_sel= 2h device id1 sfst_sel= 3h boot vector sfst_sel= 4h - - - page4 page3 page2 page1 page0 sfst_sel= 5h x boot from zero boot- from- user- vector enable clock- double disable- extern- host- cmd disable- extern- movc disable- extern- boot disable- extern- iap t3-4.0 1259 table 3-5: watchdog timer sfrs symbol description direct address bit address, symbol, or alternative port function reset value msb lsb wdtc 1 1. bit addressable sfrs watchdog timer control c0h - wdton wdfe - wdre wdts wdt swdt x0000000b wdtd watchdog timer data/reload 85h watchdog timer data/reload 00h t3-5.0 1259 table 3-6: feed sequence sfrs symbol description direct address bit address, symbol, or alternative port function reset value msb lsb sfis0 sequence reg 0 97h (write only) 00h sfis1 sequence reg 1 c4h (write only) 00h t3-6.0 1259
data sheet flashflex mcu sst89e52rc / sst89e54rc 15 ?2007 silicon storage technology, inc. s71259-04-000 1/07 table 3-7: timer/counters sfrs symbol description direct address bit address, symbol, or al ternative port function reset value msb lsb tmod timer/counter mode control 89h timer 1 timer 0 00h gate c/t# m1 m0 gate c/t# m1 m0 tcon 1 timer/counter control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h th0 timer 0 msb 8ch th0[7:0] 00h tl0 timer 0 lsb 8ah tl0[7:0] 00h th1 timer 1 msb 8dh th1[7:0] 00h tl1 timer 1 lsb 8bh tl1[7:0] 00h t2con 1 timer / counter 2 control c8h tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# 00h t2mod# timer2 mode control c9h---- - -t2oedcenxxx xxx00b th2 timer 2 msb cdh th2[7:0] 00h tl2 timer 2 lsb cch tl2[7:0] 00h rcap2h timer 2 capture msb cbh rcap2h[7:0] 00h rcap2l timer 2 capture lsb cah rcap2l[7:0] 00h t3-7.0 1259 1. bit addressable sfrs table 3-8: interface sfrs symbol description direct address bit address, symbol, or alternative port function reset value msb lsb sbuf serial data buffer 99h sbuf[7:0] indeterminate scon 1 1. bit addressable sfrs serial port control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00h saddr slave address a9h saddr[7:0] 00h saden slave address mask b9h saden[7:0] 00h p0 1 port 0 80h p0[7:0] ffh p1 1 port 1 90h - - - - - - t2ex t2 ffh p2 1 port 2 a0h p2[7:0] ffh p3 1 port 3 b0h rd# wr# t1 t0 int1# int0# txd rxd ffh t3-8.1 1259 table 3-9: clock option sfr symbol description direct address bit address, symbol, or alternative port function reset value msb lsb cosr clock option register bfh - - - - coen co_rel co_in 0x00000b
16 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 symbol function cmd_status iap command completion status 0: iap command is ignored 1: iap command is completed fully iapen iap enable bit 0: disable all iap commands (commands will be ignored) 1: enable all iap commands hwiap boot status flag 0: system boots up without special pin configuration setup 1:system boots up with both p1[0] and p1[1] pins in logic low state curing reset. (see figure 9-3.) sfst_sel provide index to read back information when read to sfst register is executed. (see , ?superflash status register (sfst) (read only register)? on page 18 for detailed settings.) superflash configuration register (sfcf) location76543210reset value b1h cmd_ status iapen - hwiap - sfst_sel 10000000b
data sheet flashflex mcu sst89e52rc / sst89e54rc 17 ?2007 silicon storage technology, inc. s71259-04-000 1/07 symbol function - reserved fcm[6:0] flash operation command 000_0001b chip-erase 000_1011b sector-erase 000_1101b partition0-erase 000_1100b byte-verify 1 000_1110b byte-program 000_0011b secure-page page-level security commands sfah=90h; secure-page0 sfah=91h; secure-page1 sfah=92h; secure-page2 sfah=93h; secure-page3 sfah=94h; secure-page4 000-0101b secure-chip chip-level security commands sfah=b0h; disable-extern-iap sfah=b1h; disable-extern-boot sfah=b2h; disable-extern-movc sfah=b3h; disable-extern-host-cmd 000-1000b boot options boot option setting commands sfah=e0h; enable-clock-double sfah=e1h; boot-from-user-vector sfah=e2h; boot-from-zero 000-1001b set-user-boot-vector all other combinations are not implemented, and reserved for future use. 1. byte-verify has a single machine cycle latency and will not generate any in t1# interrupt regardless of fie. symbol function sfal mailbox register for interfacing with flash memory block. (low order address register). symbol function sfah mailbox register for interfacing with flash memory block. (high order address register). superflash command register (sfcm) location76543210reset value b2h - fcm6 fcm5 fcm4 fcm3 fcm2 fcm1 fcm0 00h superflash address registers (sfal) location76543210reset value b3h superflash low order byte address register 00h superflash address registers (sfah) location76543210reset value b4h superflash high order byte address register 00h
18 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 symbol function sfdt mailbox register for interfacing with flash memory block. (data register). symbol function sfst this is a read-only register. the read-back value is indexed by sfst_sel in the superflash configurat ion register (sfcf). sfst_sel=0h: manufacturer?s id 1h: device id0 = f7h 2h: device id1 = device id (refer to table 4-1 on page 27) 3h: boot vector 4h: page-security bit setting 5h: chip-level security bit setting and boot options superflash data register (sfdt) location76543210reset value b5h superflash data register 00h superflash status register (sfst) (read only register) location76543 2 10reset value b6h superflash status register 10111111b
data sheet flashflex mcu sst89e52rc / sst89e54rc 19 ?2007 silicon storage technology, inc. s71259-04-000 1/07 symbol function ea global interrupt enable. 0 = disable 1 = enable et2 timer 2 interrupt enable. es serial interrupt enable. et1 timer 1 interrupt enable. ex1 external 1 interrupt enable. et0 timer 0 interrupt enable. ex0 external 0 interrupt enable. symbol function ewd watchdog interrupt enable. 1 = enable the interrupt 0 = disable the interrupt interrupt enable (ie) location76543210reset value a8h ea - et2 es et1 ex1 et0 ex0 00h interrupt enable a (iea) location76543210reset value e8h-ewd------x0 xxxxxxb
20 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 symbol function pt2 timer 2 interrupt priority bit. ps serial port interrupt priority bit. pt1 timer 1 interrupt priority bit. px1 external interrupt 1 priority bit. pt0 timer 0 interrupt priority bit. px0 external interrupt 0 priority bit. symbol function pt2h timer 2 interrupt priority bit high. psh serial port interrupt priority bit high. pt1h timer 1 interrupt priority bit high. px1h external interrupt 1 priority bit high. pt0h timer 0 interrupt priority bit high. px0h external interrupt 0 priority bit high. symbol function pwd watchdog interrupt priority bit. symbol function pwdh watchdog interrupt priority bit high. interrupt priority (ip) location76543210reset value b8h - - pt2 ps pt1 px1 pt0 px0 x0000000b interrupt priority high (iph) location76543210reset value b7h - - pt2h psh pt1h px1h pt0h px0h x0000000b interrupt priority a (ipa) location76543210reset value f8h-pwd------x0 xxxxxxb interrupt priority a high (ipah) location76543210reset value f7h-pwdh------x0 xxxxxxb
data sheet flashflex mcu sst89e52rc / sst89e54rc 21 ?2007 silicon storage technology, inc. s71259-04-000 1/07 symbol function extram internal/external ram access 0: internal expanded ram access within range of 00h to ffh using movx @ri / @dptr. beyond 100h, the mcu always accesses external data memory. for details, refer to section 3.3, ?expanded data ram addressing? . 1: external data memory access. ao disable/enable ale 0: ale is emitted at a constant rate of 1/ 3 the oscillator frequency in 6 clock mode, 1/6 f osc in 12 clock mode. 1: ale is active only during a movx or movc instruction. symbol function gf2 general purpose user-defined flag dps dptr registers select bit 0: dptr0 is selected. 1: dptr1 is selected. symbol function sfis0 register used with sfis1 to provide a feed sequence to validate writing to wdtc and sfcm. without a proper feed sequence, writing to sfcm will be ignored and writing to wdtc in wa tchdog mode will ca use an immediate watchdog reset. symbol function sfis1 register used with sfis0 to provide a feed sequence to validate writing to wdtc and sfcm. auxiliary register (auxr) location76543210reset value 8eh------extramao xxxxxx10b auxiliary register 1 (auxr1) location76543210reset value a2h----gf20-dps xxxx00x0b sequence register 0 (sfis0) location76543210reset value 97h (write only) n/a sequence register 1 (sfis1) location76543210reset value c4h (write only) n/a
22 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 symbol function wdton watchdog timer start control bit (used in watchdog mode) 0: watchdog timer can be started or stopped freely during watchdog mode. 1: start watchdog timer; bit cannot be cleared by software. wdfe watchdog feed sequence error flag 0: watchdog feed sequence error has not occurred. 1: due to an incorrect feed sequence before writing to wdtc in watchdog mode, the hardware entered watchdog reset and set this flag to ?1.? this is for software to detect whether the watchdog reset was caused by timer expiration or an incorrect feed sequence. wdre watchdog timer reset enable. 0: disable watchdog timer reset. 1: enable watchdog timer reset. wdts watchdog timer reset flag. 0: external hardware reset or power-on reset clears the flag. flag can also be cleared by writing a 1. flag survives if chip reset happened because of watchdog timer overflow. 1: hardware sets the flag on watchdog overflow. wdt watchdog timer refresh. 0: hardware resets the bit when refresh is done. 1: software sets the bit to force a watchdog timer refresh. swdt start watchdog timer. 0: stop wdt. 1: start wdt. watchdog timer control register (wdtc) location76543210reset value c0h - wdton wdfe - wdre wdts wdt swdt x0000000b
data sheet flashflex mcu sst89e52rc / sst89e54rc 23 ?2007 silicon storage technology, inc. s71259-04-000 1/07 symbol function coen clock divider enable 0: disable clock divider 1: enable clock divider co_sel clock divider selection 00b: 1/4 clock source 01b: 1/16 clock source 10b: 1/256 clock source 11b: 1/1024 clock source co_in clock source selection 0b: select clock from 1x clock 1b: select clock from 2x clock the default value of this bit is set during power-on reset by copying from enable_clock_double_i non-volatile bit setting. co_in can be changed during normal operation to select the double clock option. if the clock source is a 1x clock, the clock divider exports 1/4, 1/16, 1/256, or 1/1024 of the input clock. if the clock source is a 2x clock, the clock divider exports 1/2, 1/8, 1/128, or 1/512 of the input clock. symbol function wdu watchdog timer clock control 0:the clock for the watchdog timer is running 1:the clock for the watchdog timer is stopped tct timer 0/1 clock control 0:the timer 0/1 logic is running 1:the timer 0/1 logic is stopped tct2 timer 2 clock control 0:the timer 2 logic is running 1:the timer 2 logic is stopped pb2 further power control 2 0:the pb2 logic is running 1:the pb2 logic is stopped pb1 further power control 1 0:the pb1 logic is running 1:the pb1 logic is stopped power consumption can be decreased by setting both pb2 and pb1 to 1. uart uart clock control 0:the uart logic is running 1:the uart logic is stopped clock option register (cosr) location76543210reset value bfh---- coen co_sel co_in 00h power management control register (pmc) location76543210reset value a1h - - wdu tct tct2 pb2 pb1 uart xx000000b
24 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 symbol function smod1 double baud rate bit. if smod1 = 1, timer 1 is used to generate the baud rate, and the serial port is used in modes 1, 2, and 3. smod0 fe/sm0 selection bit. 0: scon[7] = sm0 1: scon[7] = fe, pof power-on reset st atus bit, this bit will not be affected by any other reset. pof should be cleared by software. 0: no power-on reset. 1: power-on reset occurred gf1 general-purpose flag bit. gf0 general-purpose flag bit. pd power-down bit, this bit is cleared by hardware after exiting from power-down mode. 0: power-down mode is not activated. 1: activates power-down mode. idl idle mode bit, this bit is cleared by hardware after exiting from idle mode. 0: idle mode is not activated. 1: activates idle mode. watchdog timer data/reload register (wdtd) location76543210reset value 85h watchdog timer data/reload 00h power control register (pcon) location76543210reset value 87h smod1 smod0 - pof gf1 gf0 pd idl 00x10000b
data sheet flashflex mcu sst89e52rc / sst89e54rc 25 ?2007 silicon storage technology, inc. s71259-04-000 1/07 symbol function fe set smod0 = 1 to access fe bit. 0: no framing error 1: framing error. set by receiver when an invalid stop bit is detected. this bit needs to be cleared by software. sm0 smod0 = 0 to access sm0 bit. serial port mode bit 0 sm1 serial port mode bit 1 sm2 enables the automatic address recognition feature in modes 2 or 3. if sm2 = 1 then ri will not be set unless the received 9th data bit (rb8) is 1, indicating an address, and the received byte is a given or broadcast addre ss. in mode 1, if sm2 = 1 then ri will not be activated unless a valid stop bit was received. in mode 0, sm2 should be 0. ren enables serial reception. 0: to disable reception. 1: to enable reception. tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 in modes 2 and 3, the 9th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. ti transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission, must be cleared by software. ri receive interrupt flag. set by hardware at the end of the8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software. serial port control register (scon) location76543210reset value 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00000000b sm0 sm1 mode description baud rate 1 1. f osc = oscillator frequency 0 0 0 shift register f osc /6 (6 clock mode) or f osc /12 (12 clock mode) 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /32 or f osc /16 (6 clock mode) or f osc /64 or f osc /32 (12 clock mode) 1 1 3 9-bit uart variable
26 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 symbol function tf2 timer 2 overflow flag set by a timer 2 overflow and must be cleared by software. tf2 will not be set when either rclk or tclk = 1. exf2 timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. when ti mer 2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. exf2 does not cause an interrupt in up/down counter mode (dcen = 1). rclk receive clock flag. when set, causes the se rial port to use timer 2 overflow pulses for its receive clock in modes 1 and 3. rclk = 0 causes timer 1 overflow to be used for the receive clock. tclk transmit clock flag. when set, causes the se rial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. tclk = 0 causes timer 1 overflow to be used for the transmit clock. exen2 timer 2 external enable flag. when set, allo ws a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 start/stop control for timer 2. a logic 1 starts the timer. c/t2# timer or counter select (timer 2) 0: internal timer (osc/6 in 6 clock mode, osc/12 in 12 clock mode) 1: external event counter (falling edge triggered) cp/rl2# capture/reload flag. when set, captures will occur on ne gative transitions at t2ex if exen2 = 1. when cleared, auto-reloads will occur either with ti mer 2 overflows or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forc ed to auto-reload on timer 2 overflow. symbol function - not implemented, reserved for future use. note: user should not write ?1?s to reserved bits. the value read from a rese rved bit is indeterminate. t2oe timer 2 output enable bit. dcen down count enable bit. when set, this allows timer 2 to be configured as an up/down counter. timer/counter 2 control register (t2con) location76543210reset value c8h tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# 00h timer/counter 2 mode control (t2mod) location76543210reset value c9h------t2oedcen xxxxxx00b
data sheet flashflex mcu sst89e52rc / sst89e54rc 27 ?2007 silicon storage technology, inc. s71259-04-000 1/07 4.0 flash memory programming the device internal flash memory can be programmed or erased using in-application programming (iap). 4.1 product identification the read-id command accesses the signature bytes that identify the device and the manufacturer as sst. external programmers primarily use these signature bytes in the selection of programming algorithms. 4.2 in-application programming the device offers 17/9 kbyte of in-application programma- ble flash memory. during in-application programming (iap), the cpu of the microcontroller enters stop mode. upon completion of iap, the cpu will be released to resume program execution. the mailbox registers (sfst, sfcm, sfal, sfah, sfdt and sfcf) located in the spe- cial function register (sfr), control and monitor the device?s erase and program processes. table 4-3 outlines the commands and their associated mailbox register settings. 4.2.1 iap mode clock source during iap mode, both the cpu core and the flash control- ler unit are driven off the external clock. however, an inter- nal oscillator will provide timi ng references for program and erase operations. the internal oscillator is only turned on when required, and is turned off as soon as the flash oper- ation is completed. 4.2.2 iap enable bit the iap enable bit, sfcf[6], enables in-application pro- gramming mode. until this bit is set, all flash programming iap commands will be ignored. 4.2.3 iap mode commands in order to protect the flash memory against inadvertent writes during unstable power conditions, all iap commands need the following feed sequence to validate the execution of commands. feed sequence 1. write a2h to sfis0 (097h) 2. write dfh to sfis1 (0c4h) 3. then write iap command to sfcm (0b2h) note: above commands should be executed in sequence without interference from other instructions. all of the following commands can only be initiated in the iap mode. in all situations, writing the control byte to the sfcm register will initiate all of the operations. a feed sequence is required prior to issuing commands through sfcm. without the feed sequence all iap commands are ignored. sector-erase, byte-program, and byte-verify commands will not be carried out on a specific memory page if the security locks are enabled on the memory page. the byte-program command is to update a byte of flash memory. if the original flash byte is not ffh, it should first be erased with an appropriate erase command. warning: do not attempt to write (program or erase) to a sector that the code is currently fetching from. this will cause unpredictable program behavior and may corrupt pro- gram data. table 4-1: product identification address data manufacturer?s id 30h bfh device id 31h f7h device id (extended) sst89e54rc 32h 43h sst89e52rc 32h 42h t4-1.1 1259
28 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 4.2.3.1 chip-erase the chip-erase command erases all bytes in both memory partitions. this command is only allowed when ea#=0 (external memory execution). chip-erase ignores the security setting status and will erase all settings on all pages and the different chip-level security restrictions, returning the device to its unlocked state. the chip-erase command will also erase the boot vector setting. upon completion of chip-erase command, the chip will boot from the default setting. see table 4-2 for the default boot vector setting. 4.2.3.2 partition0-erase the partition0-erase command erases all bytes in memory partition 0. all security bits associated with page0-3 are also reset. 4.2.3.3 sector-erase the sector-erase command erases all of the bytes in a sector. the sector size for the flash memory blocks is 128 bytes. the selection of the sector to be erased is deter- mined by the contents of sfah and sfal. table 4-2: default boot vector settings device address sst89e54rc 4000h sst89e52rc 2000h t4-2.1 1259 set-up mov sfdt, #55h feed sequence mov sfis0, #a2h mov sfis1, #dfh command execution mov sfcm, #01h sfcf[7] indicates operation completion iap enable orl sfcf, #40h 1259 f05.0 set-up mov sfdt, #55h iap enable orl sfcf, #40h command execution mov sfcm, #0dh sfcf[7] indicates operation completion 1259 f06.0 feed sequence mov sfis0, #a2h mov sfis1, #dfh program sector address mov sfah, #sector_addressh mov sfal, #sector_addressl command execution mov sfcm, #0bh sfcf[7] indicates operation completion 1259 f07.0 iap enable orl sfcf, #40h feed sequence mov sfis0, #a2h mov sfis1, #dfh
data sheet flashflex mcu sst89e52rc / sst89e54rc 29 ?2007 silicon storage technology, inc. s71259-04-000 1/07 4.2.3.4 byte-program the byte-program command programs data into a single byte. the address is determined by the contents of sfah and sfal. the data byte is in sfdt. 4.2.3.5 byte-verify the byte-verify command allows the user to verify that the device has correctly performed an erase or program com- mand. byte-verify command returns the data byte in sfdt if the command is successful. the previous flash operation has to be fully completed before a byte-verify command can be issued. 4.2.3.6 secure-page0, secure-page1, secure- page2, secure-page3, and secure-page4 secure-page0, secure-page1, secure-page2, secure- page3, and secure-page4 commands are used to pro- gram the page security bits. upon completion of any of these commands, th e page security options will be updated immediately. page security bits previously in un-programmed state can be programmed by these commands. the factory setting for these bits is all ?1?s which indicates the pages are not security locked. move data to sfdt mov sfdt, #data command execution mov sfcm, #0eh sfcf[7] indicates operation completion program byte address mov sfah, #byte_addressh mov sfal, #byte_addressl 1259 f08.0 iap enable orl sfcf, #40h feed sequence mov sfis0, #a2h mov sfis1, #dfh mov sfcm, #0ch sfdt register contains data program byte address mov sfah, #byte_addressh mov sfal, #byte_addressl 1259 f09.0 iap enable orl sfcf, #40h feed sequence mov sfis0, #a2h mov sfis1, #dfh select page secure_page0: mov sfah, #90h secure_page1: mov sfah, #91h secure_page2: mov sfah, #92h secure_page3: mov sfah, #93h secure_page4: mov sfah, #94h sfcf[7] indicates operation complete command execution mov sfcm, #03h 1259 f10.0 iap enable orl sfcf, #40h feed sequence mov sfis0, #a2h mov sfis1, #dfh
30 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 4.2.3.7 enable-clock-double enable-clock-double command is used to make the mcu run at 6 clocks per machine cycle. the standard (default) is 12 clocks per machine cycle (i.e. clock double command disabled). note: v il = input low voltage; v ih = input high voltage; v ih1 = input high voltage (xtal, rst); x = don?t care; al = address low order byte; ah = address high order byte; di = data input; do = data output. 4.3 in-system programming sst provides an example in-system programming (isp) solution for this device series. an example bootstrap loader can be pre-programmed into partition1 to demonstrate the initial user program code loading or subsequent user code updating via the iap operation. users can either use the sst isp solution or develop a customized isp solution. customized isp firmware can be pre-programmed into a user-defined boot vector. see sec- tion ?boot sequence? on page 40 for details. program enable-clock-double command execution mov sfcm, #08h sfcf[7] indicates operation complete 1259 f11.0 iap enable orl sfcf, #40h set-up enable-clock-double mov sfah, #e0h feed sequence mov sfis0, #a2h mov sfis1, #dfh table 4-3: iap commands operation sfcm [6:0] sfdt [7:0] sfah [7:0] sfal [7:0] chip-erase 01h 55h x x partition0-erase 0dh 55h x x sector-erase 0bh x ah al byte-program 0eh di ah al byte-verify (read) 0ch do ah al secure-page0 03h x 90h x secure-page1 03h x 91h x secure-page2 03h x 92h x secure-page3 03h x 93h x secure-page4 03h x 94h x disable-extern-iap 05h x b0h x disable-extern-boot 05h x b1h x disable-extern-movc 05h x b2h x disable-extern-host-cmd 05h x b3h x enable-clock-double 08h x e0h x boot-from-user-vector 08h x e1h x boot-from-zero 08h x e2h x set-user-boot-vector 09h di f0h x t4-3.0 1259
data sheet flashflex mcu sst89e52rc / sst89e54rc 31 ?2007 silicon storage technology, inc. s71259-04-000 1/07 5.0 timers/counters 5.1 timers the device has three 16-bit registers that can be used as either timers or event counters. the three timers/counters are denoted timer 0 (t0), timer 1 (t1), and timer 2 (t2). each is designated a pair of 8-bit registers in the sfrs. the pair consists of a most sign ificant (high) byte and least significant (low) byte. the respective registers are tl0, th0, tl1, th1, tl2, and th2. 5.2 timer set-up refer to table 3-7 for tmod, tcon, and t2con registers regarding timers t0, t1, and t2. the following tables pro- vide tmod values to be used to set up timers t0, t1, and t2. except for the baud rate generator mode, the values given for t2con do not include the setting of the tr2 bit. there- fore, bit tr2 must be set separately to turn the timer on. table 5-1: timer/counter 0 mode function tmod internal control 1 1. the timer is turned on/off by setting/clearing bit tr0 in the software. external control 2 2. the timer is turned on/off by the 1 to 0 transition on int0# (p3.2) when tr0 = 1 (hardware control). used as timer 0 13-bit timer 00h 08h 1 16-bit timer 01h 09h 2 8-bit auto-reload 02h 0ah 3 two 8-bit timers 03h 0bh used as counter 0 13-bit timer 04h 0ch 1 16-bit timer 05h 0dh 2 8-bit auto-reload 06h 0eh 3 two 8-bit timers 07h 0fh t5-1.0 1259 table 5-2: timer/counter 1 mode function tmod internal control 1 external control 2 used as timer 0 13-bit timer 00h 80h 1 16-bit timer 10h 90h 2 8-bit auto-reload 20h a0h 3 does not run 30h b0h used as counter 0 13-bit timer 40h c0h 1 16-bit timer 50h d0h 2 8-bit auto-reload 60h e0h 3 not available - - t5-2.0 1259 1. the timer is turned on/off by setting/clearing bit tr1 in the software. 2. the timer is turned on/off by the 1 to 0 transition on int1# (p3.3) when tr1 = 1 (hardware control). table 5-3: timer/counter 2 mode t2con internal control 1 1. capture/reload occurs only on timer/counter overflow. external control 2 2. capture/reload occurs on timer/counter overflow and a 1 to 0 transition on t2ex (p1.1) pin except when timer 2 is used in the baud rate generating mode. used as timer 16-bit auto-reload 00h 08h 16-bit capture 01h 09h baud rate generator receive and transmit same baud rate 34h 36h receive only 24h 26h transmit only 14h 16h used as counter 16-bit auto-reload 02h 0ah 16-bit capture 03h 0bh t5-3.0 1259
32 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 5.3 programmable clock-out a 50% duty cycle clock can be programmed to come out on p1.0. this pin, besides being a regular i/o pin, has two alternate functions. it can be programmed: 1. to input the external clock for timer/counter 2, or 2. to output a 50% duty cycle clock ranging from 122 hz to 8 mhz at a 16 mhz operating frequency (61 hz to 4 mhz in 12 clock mode). to configure timer/counter 2 as a clock generator, bit c/#t2 (in t2con) must be cleared and bit t20e in t2mod must be set. bit tr2 (t2con.2) also must be set to start the timer. the clock-out frequency depends on the oscillator fre- quency and the reload value of timer 2 capture registers (rcap2h, rcap2l) as shown in this equation: oscillator frequency n x (65536 - rcap2h, rcap2l) n = 2 (in 6 clock mode) 4 (in 12 clock mode) where (rcap2h, rcap2l) = the contents of rcap2h and rcap2l taken as a 16-bit unsigned integer. in the clock-out mode, timer 2 roll-overs will not generate an interrupt. this is similar to when it is used as a baud-rate generator. it is possible to use timer 2 as a baud-rate gen- erator and a clock generator simultaneously. note, how- ever, that the baud-rate and the clock-out frequency will not be the same. 6.0 serial i/o 6.1 full-duplex, enhanced uart the device serial i/o port is a full-duplex port that allows data to be transmitted and received simultaneously in hardware by the transmit and receive registers, respec- tively, while the software is performing other tasks. the transmit and receive registers are both located in the serial data buffer (sbuf) special function register. writ- ing to the sbuf register loads the transmit register, and reading from the sbuf register obtains the contents of the receive register. the uart has four modes of operation which are selected by the serial port mode specifier (sm0 and sm1) bits of the serial port control (scon) special function register. in all four modes, transmission is initiated by any instruction that uses the sbuf register as a destination register. reception is initiated in mode 0 when the receive interrupt (ri) flag bit of the serial port control (scon) sfr is cleared and the reception enable/ disable (ren) bit of the scon register is set. receptio n is initiated in the other modes by the incoming start bit if the ren bit of the scon register is set. 6.1.1 framing error detection framing error detection is a feature, which allows the receiving controller to check for valid stop bits in modes 1, 2, or 3. missing stops bits can be caused by noise in serial lines or from simultaneous transmission by two cpus. framing error detection is selected by going to the pcon register and changing smod0 = 1 (see figure 6-1). if a stop bit is missing, the fram ing error bit (fe) will be set. software may examine the fe bit after each reception to check for data errors. after the fe bit has been set, it can only be cleared by software. valid stop bits do not clear fe. when fe is enabled, ri rises on the stop bit, instead of the last data bit (see figure 6-2 and figure 6-3).
data sheet flashflex mcu sst89e52rc / sst89e54rc 33 ?2007 silicon storage technology, inc. s71259-04-000 1/07 figure 6-1: framing error block diagram figure 6-2: uart timings in mode 1 figure 6-3: uart timings in modes 2 and 3 1259 f12.0 sm0/fe sm1 sm2 ren tb8 rb8 ti ri smod0 smod1 pof gf1 gf0 pd idl scon (98h) pcon (87h) set fe bit if stop bit is 0 (framing error) (smod0 = 1) sm0 to uart mode control (smod0 = 0) to uart framing error control bof start bit rxd ri smod0=x fe smod0=1 d0 d1 d2 d3 d4 d5 d6 d7 data byte stop bit 1259 f13.0 start bit rxd ri smod0=1 fe smod0=1 ri smod0=0 d0 d1 d2 d3 d4 d5 d6 d7 d8 data byte ninth bit stop bit 1259 f14.0
34 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 6.1.2 automatic address recognition automatic address recognition helps to reduce the mcu time and power required to talk to multiple serial devices. each device is hooked together sharing the same serial link with its own address. in this configuration, a device is only interrupted when it receives its own address, thus eliminating the software overhead to compare addresses. this same feature helps to save power because it can be used in conjunction with idle mode to reduce the system?s overall power consumption. since there may be multiple slaves hooked up serial to one master, only one slave would have to be interrupted from idle mode to respond to the master?s transmission. automatic address recognition (aar) allows the other slaves to remain in idle mode while only one is interrupted. by limiting the number of interrup- tions, the total current draw on the system is reduced. there are two ways to communicate with slaves: a group of them at once, or all of them at once. to communicate with a group of slaves, the master sends out an address called the given address. to communicate with all the slaves, the master sends out an address called the ?broadcast? address. aar can be configured as mode 2 or 3 (9-bit modes) and setting the sm2 bit in scon. each slave has its own sm2 bit set waiting for an address byte (9th bit = 1). the receive interrupt (ri) flag will only be set when the received byte matches either the given address or the broadcast address. next, the slave then clears its sm2 bit to enable reception of the data bytes (9th bit = 0) from the master. when the 9th bit = 1, the master is sending an address. when the 9th bit = 0, the mast er is sending actual data. if mode 1 is used, the stop bit takes the place of the 9th bit. bit ri is set only when the received command frame address matches the device?s address and is terminated by a valid stop bit. note that mode 0 cannot be used. set- ting sm2 bit in the scon register in mode 0 will have no effect. each slave?s individual address is specified by sfr saddr. sfr saden is a mask byte that defines ?don?t care? bits to form the given address when combined with saddr. see the example below: 6.1.2.1 using the given address to select slaves any bits masked off by a 0 from saden become a ?don?t care? bit for the given address. any bit masked off by a 1, becomes anded with saddr. the ?don?t cares? provide flexibility in the user-defined addresses to address more slaves when using the given address. shown in the example above, slave 1 has been given an address of 1111 0001 (saddr). the saden byte has been used to mask off bits to a given address to allow more combinations of selecting slave 1 and slave 2. in this case for the given addresses, the last bit (lsb) of slave 1 is a ?don?t care? and the last bit of slave 2 is a 1. to communi- cate with slave 1 and slave 2, the master would need to send an address with the last bit equal to 1 (e.g. 1111 0001) since slave 1?s last bit is a don?t care and slave 2?s last bit has to be a 1. to communicate with slave 1 alone, the master would send an address with the last bit equal to 0 (e.g. 1111 0000), since slave 2?s last bit is a 1. see the table below for other possible combinations. if the user added a third slave such as the example below: slave 1 saddr = 1111 0001 saden = 1111 1010 given = 1111 0x0x slave 2 saddr = 1111 0011 saden = 1111 1001 given = 1111 0xx1 select slave 1 only slave 1 given address possible addresses 1111 0x0x 1111 0000 1111 0100 select slave 2 only slave 2 given address possible addresses 1111 0xx1 1111 0111 1111 0011 select slaves 1 and 2 slaves 1 and 2 possible addresses 1111 0001 1111 0101 slave 3 saddr = 1111 1001 saden = 1111 0101 given = 1111 x0x1
data sheet flashflex mcu sst89e52rc / sst89e54rc 35 ?2007 silicon storage technology, inc. s71259-04-000 1/07 the user could use the possible addresses above to select slave 3 only. another combination could be to select slave 2 and 3 only as shown below. more than one slave may have the same saddr address as well, and a given address could be used to modify the address so that it is unique. 6.1.2.2 using the broadcast address to select slaves using the broadcast address, the master can communicate with all the slaves at once. it is formed by performing a logi- cal or of saddr and saden with 0s in the result treated as ?don?t cares?. ?don?t cares? allow for a wider range in defining the broad- cast address, but in most cases, the broadcast address will be ffh. on reset, saddr and saden are ?0?. this produces an given address of all ?don?t cares? as well as a broadcast address of all ?don?t cares.? this effectively disables auto- matic addressing mode and allows the microcontroller to function as a standard 8051, which does not make use of this feature. select slave 3 only slave 2 given address possible addresses 1111 x0x1 1111 1011 1111 1001 select slaves 2 and 3 only slaves 2 and 3 possible addresses 1111 0011 slave 1 1111 0001 = saddr +1111 1010 = saden 1111 1x11 = broadcast
36 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 7.0 watchdog timer the programmable watchdog timer (wdt) is for fail safe protection against software deadlock and for automatic recovery. the watchdog timer can be utilized as a watchdog or a timer. to use the watchdog timer as a watchdog, wdre (wdtc[3]) should be set to ?1.? to use the watchdog timer as a timer only, wdre should be set to ?0? so that an inter- rupt will be generated upon timer overflow, and the ewd (iea[6]) should be set to ?1? in order to enable the interrupt. 7.1 watchdog timer mode to protect the system against software deadlock, wdt (wdtc[1]) should be refreshed within a user-defined time period. without a periodic refresh, an internal hardware reset will be initiated when wdre (wdtc[3]) = 1). the wdre bit can only be cleared by a power-on reset. any write to wdtc must be preceded by a correct feed sequence. if wdton (wdtc[6])=0, swdt (wdtc[0]) controls the start or stop of the watchdog. if wdton = 1, the watchdog starts regardless of swdt and cannot be stopped. the upper 8 bits of the time base register (wdtd) is used as the reload register of the counter. when wdt (wdtc[1]) is set to ?1,? the content of wdtd is loaded into the watchdog counter and the prescaler is also cleared. if a watchdog reset occurs, the internal reset is active for at least one watchdog clock cycle. the code execution will begin immediately after the reset cycle. the wdts flag bit is set by watchdog timer overflow and can only be cleared by power-on reset. users can also clear the wdts bit by writing ?1? to it following a correct feed sequence. 7.2 pure timer mode in timer mode, the wdtc and wdtd can be written at any time without a feed sequence. setting or clearing the swdt bit will start or stop the counter. a timer overflow will set the wdts bit. writing ?1? to this bit clears the bit. when an overflow occurs, the content of wdtd is reloaded into the counter and the watchdog timer immediately begins to count again. if the interrupt is enabled, an interrupt will occur when the timer overflows. the vector address is 053h and it has a second level priority by default. a feed sequence is not required in this mode. 7.3 clock source the wdt in the device uses the system clock (xtal1) as its time base. so strictly s peaking, it is a watchdog counter rather than a watchdog timer. the wdt register will incre- ment every 344,064 crystal clocks. the upper 8-bits of the time base register (wdtd) are used as the reload register of the wdt. figure 7-1 provides a block diagram of the wdt. two sfrs (wdtc and wdtd) control watchdog timer operation. the time-out period of the wdt is calculated as follows: period = (255 - wdtd) * 344064 * 1/f clk (xtal1) where wdtd is the value loaded into the wdtd register and f osc is the oscillator frequency. 7.4 feed sequence in watchdog mode (wdre=1), a feed sequence is needed to write into the wdtc register. the correct feed sequence is: 1. write fdh to sfis1, 2. write 2ah to sfis0, then 3. write to the wdtc register an incorrect feed sequence wi ll cause an immediate reset in watchdog mode. in timer mode, the wdtc and wdtd can be written at any time. a feed sequence is not required. 7.5 power saving considerations for using the watchdog timer during idle mode, the watchdo g timer will remain active. the device should be awakened and the watchdog timer refreshed periodically before expiration. during power- down mode, the watchdog timer is stopped. when the watchdog timer is used as a pur e timer, users can turn off the clock to save power. see ?power management control register (pmc)? on page 23.
data sheet flashflex mcu sst89e52rc / sst89e54rc 37 ?2007 silicon storage technology, inc. s71259-04-000 1/07 figure 7-1: block diagram of programmable watchdog timer 1259 f18.0 wdt upper byte wdt reset internal reset 344064 clks counter clk (xtal1) ext. rst wdtc wdtd
38 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 8.0 security lock the security lock protects against software piracy and pre- vents the contents of the flash from being read by unautho- rized parties. it also protects against code corruption resulting from accidental erasing and programming to the internal flash memory. there are two different types of security locks in the device security lock system: chip- level security lock and page-level security lock. 8.1 chip-level security lock there are four types of chip-level security locks. 1. disable external movc instruction 2. disable external host mode (except read chip id and chip-erase commands) 3. disable boot from external memory 4. disable external iap commands (except chip- erase commands) users can turn on these security locks in any combination to achieve the security protection scheme. to unlock secu- rity locks, the chip-erase command must be used. 8.1.1 disable external movc instruction when disable-extern-movc command is executed either by external host mode command or iap mode command, movc instructions executed from external program mem- ory are disabled from fetching code bytes from internal memory. 8.1.2 disable external host mode when disable-extern-host-cmd command is executed either by external host mode command or iap mode command, all external host mode commands are disabled except chip-erase command and read-id command. upon activation of this op tion, the device can not be accessed through external host mode. user can not verify and copy the contents of the internal flash 8.1.3 disable boot from external memory when disable-extern-boot command is executed either by external host mode command or iap mode command, the ea pin value will be ignor ed during chip reset and always boot from the internal memory. 8.1.4 disable external iap commands when disable-extern-iap command is executed either by external host mode command or iap mode command, all iap commands executed from external memory are dis- abled except chip-erase command. all iap commands executed from internal memory are allowed if the page lock is not set. 8.2 page-level security lock when any of secure-page0, secure-page1, secure- page2, secure-page3, or secure-page4 command is exe- cuted, the individual page (page0, page1, page2, page3, or page4) will enter secured mode. no part of the page can be verified by either external host mode commands or iap commands. movc instructions are also unable to read any data from the page. to unlock the security locks on page0-3 of the primary par- tition (partition0), the partition0-erase command must be used. to unlock the security lock on page4, the chip-erase command must be used. 8.3 read operation u nder lock condition the following three cases can be used to indicate the read operation is targeting a locked, secured memory area: 1. external host mode: read-back = 55h (locked) 2. iap command: read-back = previous sfdt data 3. movc: read-back = 00h (blank)
data sheet flashflex mcu sst89e52rc / sst89e54rc 39 ?2007 silicon storage technology, inc. s71259-04-000 1/07 9.0 reset a system reset initializes the mcu and begins program execution at program memory location 0000h or the boot vector address. the reset input for the device is the rst pin. in order to reset the device, a logic level high must be applied to the rst pin for at least two machine cycles (24 clocks), after the oscillato r becomes stable. ale and psen# are weakly pulled high during reset. during reset, ale and psen# output a high level in order to perform a proper reset. this level must not be affected by external element. a system reset will not affect the 512 bytes of on- chip ram while the device is running, however, the con- tents of the on-chip ram during power up are indetermi- nate. following reset, all s pecial function registers (sfr) return to their reset values outlined in tables 3-3 to 3-8. 9.1 power-on reset at initial power up, the port pins will be in a random state until the oscillator has started and the internal reset algo- rithm has weakly pulled all pins high. when power is applied to the device, the rst pin must be held high long enough for the oscillator to start up (usually several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid power-on reset. an exam- ple of a method to extend the rst signal is to implement a rc circuit by connecting the rst pin to v dd through a 10 f capacitor and to v ss through an 8.2k resistor as shown in figure 9-1. note that if an rc circuit is being used, provisions should be made to ensure the v dd rise time does not exceed 1 millis econd and the oscillator start- up time does not exceed 10 milliseconds. for a low frequency oscillator wi th slow start-up time the reset signal must be extended in order to account for the slow start-up time. this method maintains the necessary relationship between v dd and rst to avoid programming at an indeterminate location. the pof flag in the pcon register is set to indicate an initial power up condition. the pof flag will remain active until cleared by software. please refer to section 3.5, pcon register definition, for detailed information. for more information on system level design techniques, please review the design considerations for the sst flashflex family microcontroller application note. figure 9-1: power-on reset circuit 1259 f25.2 v dd v dd 10f + - 8.2k sst89e54rc sst89e52rc rst xtal2 xtal1 c 1 c 2
40 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 9.2 boot sequence after power on reset, the device can boot from one of three locations: zero, default boot vector (see table 4-2), or a user-defined boot vector. the checking sequence follows the flowchart in figure 9-2. if the device uses external code memory (ea#=0), the boot-start address is always zero. the next sequence is to detect any external hardware pin setup. the device should check p1[0] and p1[1] at the falling edge of reset. (see figure 9-3 for the timing diagram.) if both pins are low, the device is forced to boot from either the default boot vector or the user-defined boot vector depend- ing on the setting of boot_from_user_vector_i. the boot_status_flag bit (hwiap) in the sfcf register indi- cates whether or not the system booted with p1[0] and p1[1] set to low during reset. (see section 3.5, ?special function registers? on page 11 for details.) programming the control bits (boot_from_user_vector_i and boot_from_zero_i) can be done through iap mode commands or external host mode commands. the factory default setting for these two bits is ?1? and will lead the sys- tem to boot from the default boot vector per table 4-2. when the device is configured to boot from a user-defined vector, users should use the set_user_boot_vector com- mand to program the boot vector[7:0]. the final boot vector address is calculated in table 9-1. figure 9-2: boot sequence flowchart figure 9-3: hardware pin setup 9.3 interrupt priority and polling sequence the device supports seven interrupt sources under a four level priority scheme. table 9-2 and figure 9-4 summarize the polling sequence of the supported interrupts. table 9-1: boot vector address device bit number 1514131211109876543210 sst89e54rc 00 boot vector[7:0] 000000 sst89e52rc 0 0 0 boot vector[7:0] 0 0 0 0 0 t9-1.1 1259 power on boot_from_user_vector_i bit cleared? (=0) yes yes yes yes no boot_from_zero_i bit cleared? (=0) no default address 0 boot vector boot from external no both p1.0 and p1.1 are low? 1259 fc_boot_seq.0 no reset ea# p1.0 p1.1 1259 f26.0 300 clk 300 clk
data sheet flashflex mcu sst89e52rc / sst89e54rc 41 ?2007 silicon storage technology, inc. s71259-04-000 1/07 figure 9-4: interrupt sequence ie1 int1# individual enables tf1 tf0 ri 0 1 ie0 global disable highest priority interrupt interrupt polling sequence lowest priority interrup it0 it1 int0# ie & iea registers ip/iph/ipa/ipah registers 0 1 tf2 exf2 1259 f27.0 ti watchdog timer 1259 f27.0
42 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 table 9-2: interrupt polling sequence description interrupt flag vector address interrupt enable interrupt priority service priority wake-up power-down ext. int0 ie0 0003h ex0 px0/h 1(highest) yes watchdog - 0053h ewd pwd/h 2 no t0 tf0 000bh et0 pt0/h 3 no ext. int1 ie1 0013h ex1 px1/h 4 yes t1 tf1 001bh et1 pt1/h 5 no uart ti/ri 0023h es ps/h 6 no t2 tf2, exf2 002bh et2 pt2/h 7 no t9-2.0 1259
data sheet flashflex mcu sst89e52rc / sst89e54rc 43 ?2007 silicon storage technology, inc. s71259-04-000 1/07 10.0 power-saving modes the device provides two power saving modes of operation for applications where power consumption is critical. the two modes are idle and power-down, see table 10-1. in addition to these two power saving modes, users can choose to set the device to run at one of four slower clock rates to reduce power consumption. see section 11.3, ?clock divider option?. another option is to turn off the clocks by individual func- tional blocks, please refer to section 3.5, the pmc register definition, for detailed information. 10.1 idle mode idle mode is entered setting the idl bit in the pcon regis- ter. in idle mode, the program counter (pc) is stopped. the system clock continues to run and all interrupts and periph- erals remain active. the on-chip ram and the special func- tion registers hold their data during this mode. the device exits idle mode through either a system inter- rupt or a hardware reset. exiting idle mode via system interrupt, the start of the interrupt clears the idl bit and exits idle mode. after exit the interrupt service routine, the interrupted program resumes execution beginning at the instruction immediately following the instruction which invoked the idle mode. a hardware reset starts the device similar to a power-on reset. 10.2 power-down mode the power-down mode is entered by setting the pd bit in the pcon register. in the power-down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only. sram contents are retained during power- down, the minimum v dd level is 2.0v. the device exits power-down mode through either an enabled external level sensitive interrupt or a hardware reset. the start of the interrupt clears the pd bit and exits power-down. holding the external interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bringing back high to complete the exit. upon interrupt signal restored to logic v ih, the interrupt service routine program execution resumes beginning at the instruction immediately follo wing the instruction which invoked power-down mode. a hardware reset starts the device similar to power-on reset. to exit properly out of power-down, the reset or external interrupt should not be executed before the v dd line is restored to its normal operating voltage. be sure to hold v dd voltage long enough at its normal operating level for the oscillator to restart and stabilize (normally less than 10 ms). table 10-1: power saving modes mode initiated by state of mcu exited by idle software (set idl bit in pcon) mov pcon, #01h; ? clk is running. ? interrupts, serial port and timers/counters are active. ? program counter is stopped. ? ale and psen# signals at a high level during idle. ? all registers remain unchanged. enabled interrupt or hardware reset. start of interrupt clears idl bit and exits idle mode, after the isr reti instruction, program resumes execution beginning at the instruction following the one that invoked idle mode. a user could consider placing two or three nop instructions after the instruction that invokes idle mode to eliminate any problems. a hardware reset restarts the device similar to a power-on reset. power-down software (set pd bit in pcon) mov pcon, #02h; ? clk is stopped. ? on-chip sram and sfr data is maintained. ? ale and psen# signals at a low level during power -down. ? external interrupts are only active for level sensitive interrupts, if enabled. enabled external level sensitive interrupt or hardware reset. start of interrupt clears pd bit and exits power-down mode, after the isr reti instruction program resumes exe- cution beginning at the instruction following the one that invoked power-down mode. a user could consider placing two or three nop instructions after the instruction that invokes power-down mode to eliminate any problems. a hardware reset restarts the device similar to a power-on reset. t10-1.0 1259
44 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 11.0 system clock and clock options 11.1 clock input options and recom- mended capacitor valu es for oscillator shown in figure 11-1 are the input and output of an inter- nal inverting amplifier (xtal1, xtal2), which can be con- figured for use as an on-chip oscillator. when driving the device from an external clock source, xtal2 should be left disconnected and xtal1 should be driven. at start-up, the external oscillator may encounter a higher capacitive load at xtal1 due to interaction between the amplifier and its feedback capacitance. however, the capacitance will not exceed 15 pf once the external signal meets the v il and v ih specifications. crystal manufacturer, supply voltage, and other factors may cause circuit performance to differ from one applica- tion to another. c1 and c2 should be adjusted appropri- ately for each design. table 11-1, shows the typical values for c1 and c2 vs. crystal type for various frequencies more specific information abo ut on-chip oscillator design can be found in the flashflex oscillator circuit design considerations application note. 11.2 clock doubling option by default, the device runs at 12 clocks per machine cycle (x1 mode). the device has a clock doubling option to speed up to 6 clocks per machine cycle. please refer to table 11-2 for detail. clock double mode can be enabled either via the external host mode or the iap mode. please refer to table 4-3 for the iap mode enabling command (when set, the enable- clock-double_i bit in the sfst register will indicate 6-clock mode.). the clock double mode is only for doubling the inter- nal system clock and the internal flash memory, i.e. ea#=1. to access the external memory and the peripheral devices, careful consideration must be taken. also note that the crystal output (x tal2) will not be doubled. 11.3 clock divider option the device has an option to run at scaled-down clock rates of 1/4, 1/16, 1/256, and 1/1024. the coen bit in the cosr register must be set to enable this option. the co_sel bits are set to select the clock rate. see the cosr register for more information. figure 11-1: oscillator characteristics table 11-1:recommended values for c1 and c2 by crystal type crystal c1 = c2 quartz 20-30pf ceramic 40-50pf t11-1.1 1259 table 11-2: clock doubling features device standard mode (x1) clock double mode (x2) clocks per machine cycle max. external clock frequency (mhz) clocks per machine cycle max. external clock frequency (mhz) sst89e5xrc 12 33 6 16 t11-2.0 1259 1259 f28.0 xtal2 xtal1 v ss c 1 using the on-chip oscillator external clock drive c 2 xtal2 xtal1 v ss external oscillator signal nc
data sheet flashflex mcu sst89e52rc / sst89e54rc 45 ?2007 silicon storage technology, inc. s71259-04-000 1/07 12.0 electrical specification note: this specification contains preliminary information on new products in production. the specifications are subj ect to change without notice. absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c voltage on ea# pin to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +14.0 v d.c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20ns) on any other pin to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to v dd +1.0v maximum i ol per i/o pins p1.5, p1.6, p1.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma maximum i ol per i/o for all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ma package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5w through hole lead soldering temperature (10 seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300c surface mount solder reflow temperature 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds 1. excluding certain with-pb 32-plcc units, all packages are 260 c capable in both non-pb and with-pb solder versions. certain with-pb 32-plcc package types are capable of 240 c for 10 seconds; please consult the factory for the latest information. output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 2. outputs shorted for no more than one second. no more than one output shorted at a time. (based on package heat transfer limitati ons, not device power consumption. table 12-1: operating range symbol description min. max unit t a ambient temperature under bias standard 0 +70 c v dd supply voltage sst89e5xrc 4.5 5.5 v f osc oscillator frequency sst89e5xrc 0 33 mhz oscillator frequency for in-application programming sst89e5xrc .25 33 mhz t12-1.1 1259 table 12-2: reliability characteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t12-2.0 1259
46 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 table 12-3: ac conditions of test input rise/fall time . . . . . . . . . . . . . . . 10 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 100 pf see figures 12-6 and 12-8 t12-3.0 1259 table 12-4: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t12-4.2 1259 table 12-5: pin impedance (ta=25 c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 15 pf c in 1 input capacitance v in = 0v 12 pf l pin 2 2. refer to pci spec. pin inductance 20 nh t12-5.4 1259
data sheet flashflex mcu sst89e52rc / sst89e54rc 47 ?2007 silicon storage technology, inc. s71259-04-000 1/07 12.1 dc electrical characteristics table 12-6: dc characteristics for sst89e5xrc: t a = -0c to +70c; v dd = 4.5-5.5v; v ss = 0v symbol parameter test conditions min max units v il input low voltage 4.5 < v dd < 5.5 -0.5 0.2v dd - 0.1 v v ih input high voltage 4.5 < v dd < 5.5 0.2v dd + 0.9 v dd + 0.5 v v ih1 input high voltage (xtal1, rst) 4.5 < v dd < 5.5 0.7v dd v dd + 0.5 v v ol output low voltage (ports 1.5, 1.6, 1.7) v dd = 4.5v i ol = 16ma 1.0 v v ol output low voltage (ports 1, 2, 3) 1 1. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15ma maximum i ol per 8-bit port: 26ma maximum i ol total for all outputs:71ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. v dd = 4.5v i ol = 100a 2 2. capacitive loading on ports 0 and 2 may cause s purious noise to be superimposed on the v ol s of ale and ports 1 and 3. the noise due to external bus capacitance discharging into the port 0 and 2 pins when the pins make 1-to-0 transitions during bus operati ons. in the worst cases (capacitive loading > 100pf), the noise pulse on the ale pin may exceed 0.8v. in such cases, it may be desir able to qualify ale with a schmitt trigger, or use an ad dress latch with a schmitt trigger strobe input. 0.3 v i ol = 1.6ma 2 0.45 v i ol = 3.5ma 2 1.0 v v ol1 output low voltage (port 0, ale, psen#) 1,3 3. load capacitance for port 0, ale and psen#= 100pf, load capacitance for all other outputs = 80 pf. v dd = 4.5v i ol = 200a 2 0.3 v i ol = 3.2ma 2 0.45 v v oh output high vo ltage (ports 1, 2, 3, ale, psen#) 4 4. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen# to momentarily fall below the v dd - 0.7 specification when the address bits are stabilizing. v dd = 4.5v i oh = -10a v dd - 0.3 v i oh = -30a v dd - 0.7 v i oh = -60a v dd - 1.5 v v oh1 output high voltage (port 0 in external bus mode) 4 v dd = 4.5v i oh = -200a v dd - 0.3 v i oh = -3.2ma v dd - 0.7 v i il logical 0 input current (ports 1, 2, 3) v in = 0.4v -75 a i tl logical 1-to-0 transition current (ports 1, 2, 3) 5 5. pins of ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. the transition curre nt reaches its maximum value when v in is approximately 2v. v in = 2v -650 a i li input leakage current (port 0) 0.45 < v in < v dd -0.3 10 a r rst rst pull-down resistor 40 225 k c io pin capacitance 6 6. pin capacitance is characterized but not tested. ea# is 25pf (max). @ 1 mhz, 25c 15 pf i dd power supply current active mode @ 33 mhz 32 ma idle mode@ 33 mhz 26 ma power-down mode (min v dd = 2v) t a = 0c to 70c 50 a t12-6.1 1259
48 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 12.2 ac electrical characteristics ac characteristics: (over operating cond itions: load capacitance for po rt 0, ale#, and psen# = 100pf; load capacitance for all other outputs = 80pf) table 12-7: ac electrical characteristics t a = -0c to +70c, v dd = 4.5-5.5v@33mhz, v ss = 0v symbol parameter oscillator units 25 mhz (x1 mode) 12 mhz (x2 mode) 1 1. calculated values are for x1 mode only 33 mhz (x1 mode) 16 mhz (x2 mode) 1 variable min max min max min max 1/t clcl x1 mode oscillator frequency 025033 0 mhz 1/2t clcl x2 mode oscillator frequency 012016 0 mhz t lhll ale pulse width 65 46 2t clcl - 15 ns t avll address valid to ale low 15 t clcl - 15 (5v) ns t llax address hold after ale low 15 t clcl - 15 (5v) ns t lliv ale low to valid instr in 66 4t clcl - 45 (5v) ns t llpl ale low to psen# low 15 t clcl - 15 (5v) ns t plph psen# pulse width 76 3t clcl - 15 (5v) ns t pliv psen# low to valid instr in 41 3t clcl - 50 (5v) ns t pxix input instr hold after psen# 0ns t pxiz input instr float after psen# 15 t clcl - 15 (5v) ns t pxav psen# to address valid 32 22 t clcl - 8 ns t aviv address to valid instr in 92 5t clcl - 60 (5v) ns t plaz psen# low to address float 10 10 10 ns t rlrh rd# pulse width 152 6t clcl - 30 (5v) ns t wlwh write pulse width (we#) 152 6t clcl - 30 (5v) ns t rldv rd# low to valid data in 102 5t clcl - 50 (5v) ns t rhdx data hold after rd# 00 0 ns t rhdz data float after rd# 49 2t clcl - 12 (5v) ns t lldv ale low to valid data in 192 8t clcl - 50 (5v) ns t avdv address to valid data in 198 9t clcl - 75 (5v) ns t llwl ale low to rd# or wr# low 76 106 3t clcl - 15 (5v) 3t clcl + 15 (5v) ns t avwl address to rd# or wr# low 91 4t clcl - 30 (5v) ns t qvwx data valid to wr# high to low transition 20 10 t clcl - 20 ns t whqx data hold after wr# 10 t clcl - 20 (5v) ns t qvwh data valid to wr# high 162 7t clcl - 50 (5v) ns t rlaz rd# low to address float 00 0ns t whlh rd# to wr# high to ale high 15 45 t clcl - 15 (5v) t clcl + 15 (5v) ns t12-7.0 1259
data sheet flashflex mcu sst89e52rc / sst89e54rc 49 ?2007 silicon storage technology, inc. s71259-04-000 1/07 explanation of symbols each timing symbol has 5 characters. the fi rst character is always a ?t? (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all t he characters and what they stand for. for example: t avll = time from address valid to ale low t llpl = time from ale low to psen# low a: address q: output data c: clock r: rd# signal d: input data t: time h: logic level high v: valid i: instruction (program memory contents) w: wr# signal l: logic level low or ale x: no longer a valid logic level p: psen# z: high impedance (float)
50 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 figure 12-1: external program memory read cycle figure 12-2: external data memory read cycle 1259 f31.0 port 2 port 0 psen# ale a0 - a7 t llax t plaz t pxiz t llpl t aviv t avll t pxix t lhll t lliv t pliv t plph instr in a8 - a15 a8 - a15 a0 - a7 t pxav 1259 f32.0 port 2 port 0 rd# psen# ale t lhll p2[7:0] or a8-a15 from dph a0-a7 from ri or dpl t avdv t avwl data in instr in t rlaz t avll t llax t llwl t lldv t rlrh t rldv t rhdz t whlh t rhdx a8-a15 from pch a0-a7 from pcl
data sheet flashflex mcu sst89e52rc / sst89e54rc 51 ?2007 silicon storage technology, inc. s71259-04-000 1/07 figure 12-3: external data memory write cycle figure 12-4: external clock drive waveform table 12-8: external clock drive symbol parameter oscillator units 12mhz 33mhz variable minmaxminmax min max 1/t clcl oscillator frequency 0 40 mhz t clcl 83 30.3 ns t chcx high time 10.6 0.35t clcl 0.65t clcl ns t clcx low time 10.6 0.35t clcl 0.65t clcl ns t clch rise time 20 10 ns t chcl fall time 20 10 ns t12-8.2 1259 1259 f33.0 port 2 port 0 wr# psen# ale t lhll p2[7:0] or a8-a15 from dph a0-a7 from ri or dpl data out instr in t avll t avwl t llwl t llax t wlwh t qvwh t qvwx t whqx t whlh a8-a15 from pch a0-a7 from pcl 0.2 v dd - 0.1 0.45 v t chcl t clcl t clch t clcx t chcx 0.7v dd v dd - 0.5 1259 f34.0
52 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 figure 12-5: shift register mode timing waveforms figure 12-6: ac testing input/output test waveform figure 12-7: float waveform table 12-9: serial port timing symbol parameter oscillator units 12mhz 33mhz variable min max min max min max t xlxl serial port clock cycle time 1.0 0.364 12t clcl s t qvxh output data setup to clock rising edge 700 170 10t clcl - 133 ns t xhqx output data hold after clock rising edge 50 2t clcl - 117 ns 11 2t clcl - 50 ns t xhdx input data hold after clock rising edge 0 0 0 ns t xhdv clock rising edge to input data valid 700 170 10t clcl - 133 ns t12-9.2 1259 1259 f35.0 ale 0 instruction clock output data write to sbuf valid valid valid valid valid valid valid valid input data clear ri 01 2 34 567 t xlxl t qvxh t xhqx t xhdv t xhdx set ti set r i 1 2 3 4 5 6 7 8 v lt ac inputs during testing are driven at v iht (v dd -0.5v) for logic "1" and v ilt (0.45v) for a logic "0". measurement reference points for inputs and outputs are at v ht (0.2v dd + 0.9) and v lt (0.2v dd - 0.1) v ht v iht v ilt 1259 f36.0 note: v ht - v high test v lt - v low test v iht -v input high test v ilt - v input low test for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs, and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh = 20ma. v load +0.1v v load -0.1v v oh -0.1v timing reference points v ol +0.1v v load 1259 f37.0
data sheet flashflex mcu sst89e52rc / sst89e54rc 53 ?2007 silicon storage technology, inc. s71259-04-000 1/07 figure 12-8: a test load example figure 12-9: i dd test condition, active mode figure 12-10: i dd test condition, idle mode figure 12-11: i dd test condition, power-down mode 1259 f38.0 to tester to dut c l v dd v dd v dd v dd p0 ea# rst xtal2 (nc) clock signal all other pins disconnected xtal1 1259 f39.0 v ss i dd v dd v dd v dd p0 ea# rst xtal2 (nc) clock signal all other pins disconnected xtal1 1259 f40.0 v ss i dd table 12-10: flash memory programming/ verification parameters 1 1. for iap operations, the program execution overhead must be added to the above timing parameters. parameter 2 2. program and erase times will scale inversely proportional to programming clock frequency. max units chip-erase time 350 ms block-erase time 300 ms sector-erase time 30 ms byte-program time 3 3. each byte must be erased before programming. 100 s re-map or security bit program time 100 s t12-10.0 1259 v dd v dd v dd p0 ea# rst xtal2 (nc) all other pins disconnected xtal1 1259 f41.0 v ss i dd v dd = 2v
54 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 13.0 product ordering information device speed suffix1 suffix2 sst89 x 5xrc -xx -x -xx x x environmental attribute e 1 = non-pb package modifier i = 40 pins j = 44 leads package type n = plcc p= pdip operation temperature c = commercial = 0c to +70c operating frequency 33 = 0-33mhz 25 = 0-25mhz feature set rc = single block, dual partitions flash memory size 4 = c54 feature set + 16 kbyte 2 = c52 feature set + 8 kbyte voltage rang e e = 4.5-5.5v product series 89 = c51 core 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?.
data sheet flashflex mcu sst89e52rc / sst89e54rc 55 ?2007 silicon storage technology, inc. s71259-04-000 1/07 13.1 valid co mbinations note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. valid combinations for sst89e52rc sst89e52rc-33-c-nje sst89e52rc-33-c-pie valid combinations for sst89e54rc sst89e54rc-33-c-nje SST89E54RC-33-C-PIE
56 data sheet flashflex mcu sst89e52rc / sst89e54rc ?2007 silicon storage technology, inc. s71259-04-000 1/07 14.0 packaging diagrams figure 14-1: 40-pin plastic dual in-line pins (pdip) sst package code: pi figure 14-2: 44-lead plastic lead chip carrier (plcc) sst package code: nj 40-pdip-pi-7 pin #1 identifier c l 40 1 base plane seating plane .220 max. 12? 4 places .600 bsc .100 bsc .100 ? .200 .015 .022 .045 .055 .063 .090 .015 min. .065 .075 2.020 2.070 .008 .012 0? 15? .600 .625 .530 .557 note: 1. complies with jedec publication 95 ms-011 ac dimensions (except as noted), although some dimensions may be more strin gent. ? = jedec min is .115; sst min is less stringent 2. all linear dimensions are in inches (min/max). 3. dimensions do not include mold flash. maximum allowable mold flash is .010 inches. .025 .045 .013 .021 .590 .630 .100 .112 .020 min. .165 .180 top view side view bottom view 144 .026 .032 .500 ref. 44-plcc-nj-7 note: 1. complies with jedec publication 95 ms-018 ac dimensions (except as noted), although some dimensions may be more strin gent. ? = jedec min is .650; sst min is less stringent 2. all linear dimensions are in inches (min/max). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc. .050 bsc. .026 .032 .042 .056 .646 ? .656 .042 .048 .042 .048 optional pin #1 identifier .646 ? .656 .685 .695 .685 .695 .020 r. max. .147 .158 r. x45?
data sheet flashflex mcu sst89e52rc / sst89e54rc 57 ?2007 silicon storage technology, inc. s71259-04-000 1/07 table 14-1: revision history number description date 00 ? initial release of fact sheet feb 2005 01 ? added 40-pdip devices and associated mpns. ? revised function block and pin assignment diagrams. ? revised valid combinations product numbers. ? removed 4kbyte product from the fact sheet (sst89x51rc). ? initial release of data sheet feb 2006 02 ? revised factory pre-programed bsl statements to pre-programming by user capa- bilities, pages 1 and 30. ? changed 17/9/5 to 17/9 in first paragraph of section 4.2 on page 27. ? changed 2fffh to 3fffh in figure 3-2 on page 11. ? removed industrial (-40c to +85c) from temperature range on page 1, and operation temperature on page 55. ? changed t a = -40c to +85c to t a = -0c to +70c in tables 12-6, 12-7, and 12-8 ? removed 44-lead tqfp from package available page 1 and tq = tqfp from package type on page 55. ? removed ?i? and ?tqje? packages from valid combinations on page 56. ? removed package diagram for tqfp, figure 14-3 on page 58. ? globally removed all 3v (sst89v52rc/sst89v54rc) references. ? removed pin assignment for 44-lead tqfp on page 6. ? edited tables 4.-2, 4-3 (page 28), 9-1, (page 40), 11-2 (page 44), 12-1(page 45), 12-5 (page 46), and 12-7 (page 48) to remove 3v / 89v52ec references. ? removed the entire ?dc characteristics for sst89v5xrc...? table. ? removed sst89v52rc and sst89v54rc valid combinations page 55. ? removed 44-lead thin quad flat pack (tqfp) package drawing. ? edited figures 3-2 and 9-1 to remove 3v / 89v52ec. mar 2006 03 ? changed reset value from 01x0x000b to 10000000b in table 3-4, page 14. ? changed reset value from 01x0x000b to 10000000b in sfcf register, page 16. ? changed reset value from xxxxx0xxb to 1011111b in sfcf register, page 18. ? changed external host mode: read-back = 00h to 55h, page 38. ? changed movd: read-back = ffh to 00h, page 38. ? changed document status from preliminary specification to data sheet. may 2006 04 ? changed flashflex51 to flashflex globally jan 2007 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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